Layout Design of a 2-bit Binary Parallel Ripple Carry Adder Using CMOS NAND Gates with Microwind

Abstract

A good deal of ingenuity can be exercised and a vast amount of time wasted exploring layout topologies to minimize the size of a gate or other circuitry such as an adder or memory element in an integrated circuit. This paper represents a simple and compact layout design for two bit binary parallel ripple carry adder using only CMOS NAND gates with the help of Microwind as a tool for design and simulation. Construction of this adder for fabricating involves the design of 2-input, 3-input, 4-input NAND gates and CMOS NAND inverters. The performance parameters are analyzed from the simulation responses and characteristics curves of the proposed design. The optimization of the design towards single P⁺ or N⁺ diffusion, single +V_dd and single –V_dd supply contributed to lesser area and improved functionality of the adder circuits performance.